A modem semiconductor device is component of approximately 20-30 pattern layers that collectively implement the intended functionality of the designer. In general, the designer describes the chip functionality with high level, behavior design languages like VHDL, and then a series of EDA tools translate the high-level description into a GDSII file. The GDSII file contains a geometrical description of polygons and other shapes that describe the patterns of the different layers. The GDSII file accompanied with process design rules for the fabrication process to be used to make the device describes the intended geometry on the layout with the relevant tolerances.
Modern photolithography presents several challenges, including those associated with moving from 90 nm to 45 nm and 32 nm while keeping the stepper wavelengths at 193 nm. This requires further transformation of the intended layout geometry to a post resolution enhancement technique (RET) version of the GDSII file. The new GDSII file includes pattern modifications for optical proximity corrections (OPC) and mask technology. The complex set of OPC corrections, mask-making and stepper conditions is required to print the intended geometry on the wafer.
In light of the above, semiconductor technologies have created a high demand for structuring and probing specimens within the nanometer scale. Micrometer and nanometer scale process control, inspection or structuring, is often done with charged particle beams. Probing or structuring is often performed with charged particle beams which are generated and focused in charged particle beam devices. Examples of charged particle beam devices are electron microscopes, electron beam pattern generators, ion microscopes as well as ion beam pattern generators. Charged particle beams, in particular electron beams, offer superior spatial resolution compared to photon beams, due to their short wavelengths at comparable particle energy.
For semiconductor manufacturing, throughput can be a significant limitation in tools for scanning a geometry in its entirety. Assuming a CD-SEM resolution of 1 nm, a 10 mm2 die contains 10E14 pixels. Accordingly, for covering the entire layout, a parallel architecture is desired.
Electron beam systems for multiple electron beams, which may be used for a fast wafer inspection, are generally realized by either an array of conventional single beam columns having a spacing in the range of a few centimeters or by a single column with an array of beams. In the latter case, the beam array has relatively small electron beam spacing in a range of 10 μm-100 μm. Thereby, a high number such as hundreds or even thousands of beams can be used. However, individual corrections of the beams are difficult.
In order to provide a tool that utilizes electron beam optics to scan the entire geometry of the chip layer within resolution and desired signal to noise ratio (SNR), which enables extraction and verification of the wafer pattern geometry against the design-intended GDSII file, i.e. the original GDSII file, improved and different system designs have to be considered.